You can make the LogicCom compiler with the usual command - from your work directory:
CMAKE LogicCom
You can compile one of these programs and look at the generated code with a batch command like the following (without running the program):
COMPILE examples\egxx (for example COMPILE examples\eg02)
You can compile and then immediately execute a program with a batch command like
RUN examples\egxx (for example RUN examples\eg05)
Or you can run the LogicCom compiler in the usual sort of way:
LogicCom eg05.log LogicCom eg05.log -l (to merge the error messages)
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$C+ // minimal empty program (completely empty source file
// eg00.log
// You should be able to generate eg00.cod on the following lines
// Of course the label main will be replaced by the numeric address 6
// DSP 0 // no global variables needed
// FHDR
// CALL main // call "main"
// HALT // and exits the program
// main DSP 26 // main allocates space for 26 local variables a ... z
// // (their offsets are 4 ... 29)
// RETV // empty main simply returns from a void function
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$C+ // traditional hello world
// eg01.log
write("Hello world");
// You should be able to generate eg01.cod on the following lines
// DSP 0 // no global variables needed
// FHDR
// CALL main // call "main"
// HALT // and exits the program
// main DSP 26 // main allocates space for 26 local variables a ... z
// PRNS "Hello world" // give a cheerful greeting
// RETV // and simply return
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$C+ // minimal use of a variable
// eg02.log
a = true;
write(a, not a); // true false. Amazing?
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$C+ // writing constants
// eg03.log
write(true, false);
// DSP 0
// FHDR
// CALL main
// HALT
// main DSP 26
// LDC 1 // push true
// PRNB // write(true)
// LDC 0 // push false
// PRNB // write(false)
// RETV
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$C+ // writing negated constants
// eg04.log
write(not true, not not false);
// DSP 0
// FHDR
// CALL main
// HALT
// main DSP 26
// LDC 1 // true
// NOT // not true
// PRNB
// LDC 0 // false
// NOT
// NOT // not not false
// PRNB
// RETV
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$C+ // minimal read/write
// eg05.log
read(a); // t or true or f or false
write(a, not a);
// Of course the label will be replaced by a numeric address (6)
// and the variable name a by the appropriate offset from FP (4).
// DSP 0
// FHDR
// CALL main
// HALT
// main DSP 26
// LDA a // push address(a)
// INPB // read(a)
// LDL a // push value(a)
// PRNB // write(a)
// LDL a // push value(a)
// NOT
// PRNB // write(not a)
// RETV
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$C+ // simple expressions
// eg06.log
a = true;
b = false;
write(a, b, "a and b", a and b, "a or b", a or b);
// Of course the labels will be replaced by numeric addresses
// and the variable names a,b by the appropriate offsets from FP.
// DSP 0
// FHDR
// CALL main
// HALT
// main DSP 26 // a,b,c ... at offsets 4,5,6 ...
// LDC 1
// STL a // a = true
// LDC 0
// STL b // b = false
// LDL a
// PRNB // write(a)
// LDL b
// PRNB // write(b)
// PRNS "a and b"
// LDL a
// LDL b
// AND
// PRNB // write(a and b)
// PRNS "a or b"
// LDL a
// LDL b
// OR
// PRNB // write(a or b)
// RETV
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$C+ // interesting expressions (1) - predict the output
// eg07.log
read("supply a, b and c ", a, b, c); // t or true or f or false
f = a or b or c;
d = (a or b) or c;
e = a or (b or c);
write(d, e, f, f == d, d == e, e == f, c == d == e);
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$C+ // interesting expressions (2) - predict the output
// eg08.log
read("supply a, b and c ", a, b, c); // t or true or f or false
f = a or b or c;
d = (a or b) or c;
e = a or (b or c);
write(d, e, f, f == d, d == e, e == f, c == d == not e);
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$C+ // interesting expressions (3) - predict the output
// eg09.log
read("supply a, b and c ", a, b, c); // t or true or f or false
f = a and b and c;
d = (a and b) and c;
e = a and (b and c);
write(d, e, f, f == d, d == e, e == f, c == d == e);
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$C+ // minimal function (no parameters)
// eg10.log
NOT() returns true;
// DSP 0
// FHDR
// CALL main // call main
// HALT
// NOT LDC 1 // NOT starts here
// STL 0 // stores true in RV slot at base of stack frame
// RET // and returns from non-void function
// TRAP // safety feature (is this needed?)
// main DSP 26 // main starts here
// RETV // and simply returns
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$C+ // multiple choice strategy?
// eg11.log
Guess() returns true or false;
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$C+ // rather redundant, but legal function
// eg12.log
NOT(x) returns not x;
// Of course the labels will be replaced by numeric addresses
// and the parameter name x by the appropriate offset from FP.
// DSP 0
// FHDR
// CALL main // call main
// HALT
// NOT LDL x // push value(x)
// NOT // not x
// STL 0 // // stores not x in RV slot at base of stack frame
// RET // return from non-void function
// TRAP
// main DSP 26 // main starts here
// RETV // and simply returns
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$C+ // rather redundant, but legal function
// eg13.log
Ident(x) returns x;
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$C+ // the dreaded NAND gate for beginners
// eg14.log
NAND(x, y) returns not ( x and y );
read("supply a and b ", a, b); // t or true or f or false
write(a, b, a and b, NAND(a, b));
// Of course the labels will be replaced by numeric addresses,
// the parameter names x,y by appropriate offsets from FP
// and the variable names a,b by appropriate offsets.
// DSP 0
// FHDR
// CALL main // call main
// HALT
// NAND LDL x // NAND starts here
// LDL y
// AND // x and y
// NOT // not (x and y)
// STL 0 // store in RV slot at base of stack frame
// RET // return from non-void function
// TRAP
// main DSP 26 // main starts here
// PRNS "supply a and b "
// LDA a
// INPB // read(a)
// LDA b
// INPB // read(b)
// LDL a
// PRNB // write(a)
// LDL b
// PRNB // write(b)
// LDL a
// LDL b
// AND
// PRNB // write(a and b)
// FHDR
// LDL a // push argument value(a)
// LDL b // push argument value(b)
// CALL NAND // call NAND(a, b)
// PRNB // write (NAND(a, b)
// RETV
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$C+ // NAND and XOR are often used logic gates
// eg15.log
NAND(x, y) returns not ( x and y );
XOR(p, q) returns p and not q or q and not p;
read("supply a and b ", a, b);
write(a, b, a and b, NAND(a, b), XOR(a, b), XOR(b, a) );
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$C+ // minimal functions
// eg16.log
NAND1(x, y) returns not ( x and y );
NAND2(x, y) returns not x or not y ; // de Morgan
read("supply a and b ", a, b);
write(a, b, a and b, NAND1(a, b), NAND2(a, b) );
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$C+ // NOR in two ways - are they equivalent? // eg17.log
// eg17.log
NOR1(x, y) returns not ( x or y );
NOR2(x, y) returns not x and not y ; // de Morgan
read("supply a and b ", a, b);
write(a, b, a or b, NOR1(a, b), NOR2(a, b) );
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$C+ // NOR functions called with constant arguments
// eg18.log
NOR1(x, y) returns not ( x or y );
NOR2(x, y) returns not x and not y ; // de Morgan
write(NOR1(true, true), NOR2(true, true) );
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$C+ // compounded functions
// eg19.log
NOR(x, y) returns not ( x or y );
read("supply a, b, c ", a, b, c);
write(a, b, c, NOR(a, NOR(b, c)) );
// DSP 0
// FHDR
// CALL main // call main
// HALT
// NOR LDL x // NOR starts here
// LDL y
// OR // x or y
// NOT // not (x or y)
// STL 0 // store in RV slot at base of stack frame
// RET // return from non-void function
// TRAP
// main DSP 26 // main starts here
// PRNS "supply a, b, c "
// LDA a
// INPB // read(a)
// LDA b
// INPB // read(b)
// LDA c
// INPB // read(c)
// LDL a
// PRNB // write(a)
// LDL b
// PRNB // write(b)
// LDL c
// PRNB // write(c)
// FHDR // frame header for "first" NOR
// LDL a // push parameter a
// FHDR // prepare frame header for "second" NOR
// LDL b // push parameter b
// LDL c // push parameter c
// CALL NOR // returns NOR(b, c)
// CALL NOR // returns NOR(a, NOR(b,c))
// PRNB // write(NOR(a, NOR(b, c))
// RETV // wasn't that cute?
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$C+ // XOR and NAND again
// eg20.log
XOR(p, q) returns p and not q or q and not p;
NAND(x, y) returns not ( x and y );
read("supply a and b ", a, b);
write(a, b, a and b, NAND(a, b), XOR(a, b), XOR(b, a) );
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$C+ // three input AND gate
// eg21.log
AND3(p, q, r) returns p and q;
read("supply a, b and c ", a, b, c);
write(a, b, c, AND3(a, b, c));
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$C+ // three input and gate
// eg22.log
AND3(p, q, r) returns p and q;
read("supply a, b and c ", a, b, c);
write(a, b, c, AND3(a, b, c, d));
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$C+ // clearly wrong syntax - what happens? (you need more of these)
// How many errors are reported? All of them?
// eg23.log
AND3{p, q, r} returns p and q;
BUT[s,d] returns true;
read("supply a, b and c ", a, b, c);
write(a, b, c, AND3(a, b; c));
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$C+ // how does this handle life?
// How many errors are reported? All of them?
// eg24.log
AND(p, q) returns 0;
BUT(d, e) returns -45;
YES(no) returns - no - no;
GoneBlank returns ;
read("supply a, b and c ", a, b, c);
write(a, b, c, AND(a, b c), YES(a or not a));
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$C+ // complete functions
// eg25.log
// Do you recall your logic lectures?
// A supply of NAND gates allows you to build circuits for AND, OR, NOT
// from NAND gates suitably wired together
NAND(p, q) returns not (p and q);
read("supply a and b ", a, b);
write(a, b,
a or b, NAND( NAND(a, a), NAND(b, b) ),
not a, NAND( a, a ),
a and b, NAND( NAND(a, b), NAND(a, b) ) );
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$C+ // truth tables - simplest case
// eg26.log
loop x
write(x);
// writes false true as x cycles through these two values
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$C+ // truth tables - double (nested) loop
// eg27.log
loop x
loop y
writeLine(x, y);
// false false
// false true
// true false
// true true
//
//
// 74 operations.
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$C+ // truth tables - triple (nested) loop
// eg28.log
loop x
loop y
loop z
writeLine(x, y, z);
// false false false
// false false true
// false true false
// false true true
// true false false
// true false true
// true true false
// true true true
//
// 174 operations.
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$C+ // truth tables
// eg29.log
XOR(x, y) returns x and not y or y and not x;
NAND(x, y) returns not (x and y);
writeLine(" x y x xor y not x or not y");
writeLine();
loop x
loop y {
writeLine(x, y, " ", XOR(x, y), " ", NAND(x, y));
writeLine();
}
// x y x xor y not x or not y
//
// false false false true
//
// false true true true
//
// true false true true
//
// true true false false
//
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$C+ // truth tables for complete functions
// eg30.log
NAND(p, q) returns not (p and q);
loop a
loop b
writeLine(a, b,
" a or b : ", a or b, NAND( NAND(a, a), NAND(b, b) ),
" not a : ", not a, NAND( a, a ),
" a and b : ", a and b, NAND( NAND(a, b), NAND(a, b) ) );
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$C+ // NAND in two ways - are they equivalent?
// eg31.log
NAND1(x, y) returns not ( x and y );
NAND2(x, y) returns not x or not y ; // de Morgan
loop a
loop b
writeLine(a, b, a and b, NAND1(a, b), NAND2(a, b), NAND1(a, b) == NAND2(a, b) );
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$C+ // NOR in two ways - are they equivalent?
// eg32.log
NOR1(x, y) returns not ( x or y );
NOR2(x, y) returns not x and not y ; // de Morgan
loop a
loop b
writeLine(a, b, a or b, NOR1(a, b), NOR2(a, b), NOR1(a, b) == NOR2(a, b) );
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